1. Field of the Invention
The present invention relates to the provision of a bond pad for effecting through-wafer connections to an integrated circuit or electronic package, and which pad comprises a high surface area aluminum bond pad in order to resultingly obtain a highly reliable, low resistance connection between bond pads and electrical leads.
In the current state-of-the-technology, through-wafer connections are frequently employed in the formation of advanced types of electronic packages, for instance, such as, but not limited to, 3D packaging, MEMS packaging, or CMOS imager packaging. In particular, the process which is utilized for these connections is designed to etch a via through the rear side of the wafer and through the bond pads, so as to expose the edges of the respective bond pads. Leads are then formed so as to connect the edges of the bond pads to solder bumps, which are arranged on the rear sides of the electronic package. Thus, for multilevel aluminum (Al) wiring, multiple levels are employed in order to form the connection between the leads and the bond pads so as to be able to obtain low resistance electrical connections. However, when employing (Cu) copper wiring, this particular approach is subject to a poor or relatively low degree of reliability in the use of multiple Cu levels to form connections between the bond pads and leads, as a consequence of oxidation and corrosion of the copper material. A single aluminum pad is frequently employed as a final metal layer in Cu interconnect processes. Nevertheless, the use of such a single aluminum bond pad in effecting a connection to the leads may result in the formation of a high resistance connection, which has an adverse effect on reliability and may generate a high degree of heat shortening the service life of the electronic package in which it is installed.
Various aspects of the applicable technology have been developed, and prior art publications are in existence, which address themselves to the concept of employing vias under bond pads to provide for through-wafer connections or for the protection of underlying dielectrics. However, these constructions require either an extra mask, for instance, such as for through-wafer connections, or alternatively, necessitate that a metal layer be arranged beneath the via for the protection of underlying dielectrics.
2. Discussion of the Prior Art
Chisholm, et al., U.S. Pat. No. 6,586,839 B2 disclose the provision of vias beneath bond pads, which vias are intended to protect low-k dielectrics from sustaining any damage. These vias land on the underlying metal; and are required to employ this structure in order to mechanically strengthen the latter. This, however, requires the provision of arranging metal below the vias, inasmuch as such metal would of necessity be copper and would be subject to being exposed to ambient conditions and thereby susceptible to corrosion. In contrast to this prior art, which is plainly used for mechanical or structural integrity of low-k dielectrics beneath a bond pad, the inventive approach is intended to improve the electrical characteristics and increase cross section area of contacts from pads to leads on the backside of wafer.
Rolfson, U.S. Pat. No. 6,060,378 discloses the formation of a thick bond pad by adding a dielectric and a mask, and forming a thick damascene metal pad on top of a standard bond pad. Although this is somewhat similar to a general aspect of the present invention, in which the latter adds metal to the top of a bond pad using a shadow mask or selective plating, in contrast with the prior art the inventive approach resides in that there is an elimination of any deposit of additional layers over the remainder of the chip, inasmuch as such additional layers would be detrimental to the microlens, or similar MEMS structures.
With regard to the disclosures of Siniaguine, U.S. Pat. No. 6,639,303 B2; Cheng, et al., U.S. Patent Publication No. 2004/0141421 A1; and Pogge, et al., U.S. Patent Publication No. 2004/0097002 A1, these all require the application of an extra mask in order to produce through wafer vias below a bond pad. These vias extend all the way through a silicon wafer, whereas contrastingly, pursuant to the invention the via only extends through the dielectric on top of the silicon (Si), so as to structurally, distinguish over these patent publications.